The present invention relates to semiconductor devices and methods of fabricating the same and, more particularly, to phase change memory devices and methods of fabricating the same.
Phase change memory devices are a type of nonvolatile memory device which retain their stored data even when their power supplies are interrupted. The phase change memory devices may employ a phase change material as a data storage element having two stable states. The phase change material may exhibit one of two stable states, for example, an amorphous state or a crystalline state according to a temperature of the phase change material and a time period within which the temperature is maintained. The phase change material having the amorphous state may exhibit a higher resistivity than that of the phase change material having the crystalline state.
The phase change memory device may have a plurality of unit cells, and each of the unit cells may include the phase change material layer. The phase change memory cell may be programmed by heating the phase change material layer to have one of the two stable states, and the data stored in the programmed cell may be read out by discriminating whether or not a first current flowing through a selected unit cell is higher than a second current flowing through a reference cell. For example, the data stored in the selected unit cell may be regarded as a logic “1” when the first current is higher than the second current, and the data stored in the selected cell may be regarded as a logic “0” when the first current is lower than the second current. An alloy material containing germanium (Ge), stibium (Sb) and tellurium (Te) (hereinafter, referred to as “GST”) is widely used as the phase change material.
In general, the unit cell of the phase change memory device may include a GST pattern and a conductor heating the GST pattern.
FIG. 1 is a cross sectional view illustrating a unit cell of a conventional phase change memory device.
Referring to FIG. 1, an interlayer oxide layer 2 is disposed on an integrated circuit substrate such as a semiconductor substrate 1, and a titanium nitride (TiN) plug 3 may be disposed to penetrate the interlayer oxide layer 2. A GST pattern 4 and a conductive pattern 5 are sequentially stacked on the interlayer oxide layer 2. The GST pattern 4 may be in contact with a top surface of the TiN plug 3.
In the conventional phase change memory device described above, a program current may be supplied to flow through the TiN plug 3, the GST pattern 4 and the conductive pattern 5. The program current flowing through the TiN plug 3 may generate joule heat, and the GST pattern 4 may be heated up to a predetermined temperature by the joule heat. The GST pattern 4 may be changed into an amorphous state or a crystalline state according to the temperature of the GST pattern 4 and a time period within which the temperature is maintained. Typically, the joule heat may be generated at a vicinity of an interface 6 between the TiN plug 3 and the GST pattern 4. This is because an area of the interface 6 between the TiN plug 3 and the GST pattern 4 is often less than that of the interface between the GST pattern 4 and the conductive pattern 5.
When the program operation is repeatedly performed on a specific phase change memory cell, the interface characteristic between the GST pattern 4 and the TiN plug 3 of the specific phase change memory cell may be degraded. For example, when the number of the program operation is increased, adhesion between the GST pattern 4 and the TiN plug 3 may be weakened to cause a lifting phenomenon of the GST pattern 4. As a result, the endurance characteristic of the phase change memory device may be significantly degraded.